Product overview

Part Number
7202LA12PDG
Manufacturer
Renesas / IDT
Product Category
FIFO
Description
FIFO 1K X 9 CMOS PARALLEL FIFO

Documents & Media

Datasheets
7202LA12PDG

Product Attributes

Access Time :
12 ns
Maximum Clock Frequency :
50 MHz
Maximum Operating Temperature :
+ 70 C
Memory Size :
9 kbit
Minimum Operating Temperature :
0 C
Organization :
1 k x 9
Package / Case :
PDIP-28
Packaging :
Tube
Supply Current - Max :
80 mA
Supply Voltage - Max :
5.5 V
Supply Voltage - Min :
4.5 V

Description

FIFO 1K X 9 CMOS PARALLEL FIFO

Price & Procurement

Associated Product

  • Xilinx
    CPLD - Complex Programmable Logic Devices XC2C256-6VQG100C
  • Xilinx
    CPLD - Complex Programmable Logic Devices XC2C256-6TQG144C
  • Xilinx
    CPLD - Complex Programmable Logic Devices 3.3V 36-mc CPLD
  • Xilinx
    CPLD - Complex Programmable Logic Devices XC2C32A-6VQG44C
  • Xilinx
    CPLD - Complex Programmable Logic Devices 3.3V 72-mc CPLD
  • Xilinx
    CPLD - Complex Programmable Logic Devices XC2C64A-7VQG44C
  • Xilinx
    CPLD - Complex Programmable Logic Devices 3.3V 72-mc CPLD
  • Xilinx
    CPLD - Complex Programmable Logic Devices XC2C64A-7VQG44I
  • STMicroelectronics
    Microprocessors - MPU MPU ARM926 Cortex 8-ch DMA 32KB Rom
  • STMicroelectronics
    Embedded - CPLDs (Complex Programmable Logic Devices)

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